The present invention relates generally to integrated circuit devices, and, more particularly, to a method and apparatus for implementing multiple column redundancy for memory.
Static Random Access Memories (SRAMs) are memory elements that store data in the form of complementary low voltage and high voltage at opposite sides of the memory cell. An SRAM retains the memory value therein so long as power is applied to the circuit, unlike dynamic random access memory (DRAM) that must be periodically refreshed in order for the data to be maintained therein. Conventionally, if the “true” node of an SRAM is read as a high voltage, then the value of the SRAM cell is logical one. Conversely, if the true node is read as a low voltage, the value of the SRAM cell is logical zero.
Due to the high degree of miniaturization possible today in semiconductor technology, the size and complexity of designs that may be implemented in hardware has increased dramatically. This has made it technologically feasible and economically viable to develop high-speed, application specific architectures featuring a performance increase over previous architectures. Process scaling has been used in the miniaturization process to reduce the area needed for both logic functions and memory (such as SRAM) in an effort to lower the product costs.
In order to improve the yield of high-speed, high-density SRAM products, redundant elements are incorporated into the devices. These redundant elements may include for example, row elements, column elements, or both. Generally speaking, the larger the SRAM device, the more repair actions are likely needed for yield improvement. With the availability of multiple row and column repair actions, yield is significantly improved since there is greater flexibility in dealing with the various defect mechanisms. However, one problem associated with multiple repair actions is the difficulty in managing multiple column repair actions, since the outputs of the columns are not decoded and because conventional multiplexing schemes result in performance loss. Moreover, for any amount of column redundancy implemented, the multiplexing must be performed on both column inputs and outputs.
Accordingly, it would be desirable to be able to implement a multiple column redundancy repair scheme in a manner that reduces device real estate and that also minimizes the impact on device performance.